1. Field of the Invention
The present disclosure relates a semiconductor device and a fabricating method thereof.
2. Description of the Related Art
Presently, in Back-End-of-Line (BEOL) processes, after a semiconductor device has been formed it is necessary to form an insulating layer on the active region layer of the semiconductor device. Contacts to the active region are formed by making connection holes in the insulating layer in at least a portion of the active region, and then filling the connection holes with a metal material.
FIG. 1a and FIG. 1b illustrate a method for forming the above contacts with a Damascene process in the prior art.
First of all, an insulating layer 101 is etched to form connection holes 102, so that an active region (not shown in the figure) is exposed, as shown in FIG. 1a. 
The connection holes 102 are filled with a metal material to form contacts 103 to the active region. Next, chemical mechanical polishing is performed to planarize the surface of the semiconductor device that has been formed, as shown in FIG. 1b. 
In FIG. 1a, the reference label 104 indicates a photoresist layer, and the reference label 106 represents an interlayer, and reference label 105 represents a structure, for instance a gate, of a semiconductor device.
With the development of semiconductor fabrication industry, the size of semiconductor devices designed and fabricated is becoming smaller and smaller, leading to the further scaling-down in width of the active contacts 103. The effect of dual stress liner (DSL) on channel stress enhancement has been greatly reduced, which may cause the degradation of channel stress performance.
In order to overcome such a defect, a technical solution of tensile trench contact has been proposed to enhance channel stress for N-MOS (Negative-Mental-Oxide-Semiconductor). However, such a solution does not produce a satisfied effect. Meanwhile, this solution is only applicable to N-MOS, and is unsuitable for P-MOS (Positive-Mental-Oxide-Semiconductor).